View WS57C45-25_142678.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

WS57C45 HIGH-SPEED 2K x 8 REGISTERED CMOS PROM/RPROM
KEY FEATURES
* Ultra-Fast Access Time
-- 25 ns Setup -- 12 ns Clock to Output
* DESC SMD Nos. 5962-88735/5962-87529 * Pin Compatible with AM27S45 and
CY7C245 * Immune to Latch-UP
-- Up to 200 mA
* Low Power Consumption * Fast Programming * Programmable Synchronous or
Asynchronous Output Enable
* ESD Protection Exceeds 2000 V * Programmable Asynchronous Initialize
Register
GENERAL DESCRIPTION
The WS57C45 is an extremely High Performance 16K UV Erasable Registered CMOS RPROM. It is a direct drop-in replacement for such devices as the AM27S45 and CY7C245. To meet the requirements of systems which execute and fetch instructions simultaneously, an 8-bit parallel data register has been provided at the output which allows RPROM data to be stored while other data is being addressed. An asynchronous initialization feature has been provided which enables a user programmable 2049th word to be placed on the outputs independent of the system clock. This feature can be used to force an initialize word or provide a preset or clear function. A further advantage of the WS57C45 over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology. This enables the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike devices which cannot be erased, every WS57C45 RPROM in a windowed package is 100% tested with worst case test patterns both before and after assembly.
PIN CONFIGURATION
TOP VIEW Chip Carrier
NC
CERDIP/Plastic DIP/ Flatpack
A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 A10 INIT/VPP OE/OES CP/PGM O7 O6 O5 O4 O3
A5 A6 A7 432
VCC A8 A9
A4 A3 A2 A1 A0 NC O0
28 27 26 1 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 O1 O2 NC O3 O4 O5
A10 INIT/VPP OE/OES CP/PGM NC O7 O6
GND
PRODUCT SELECTION GUIDE
PARAMETER Set Up Time (Max) Clock to Output (Max) WS57C45-25 25 ns 12 ns WS57C45-35 35 ns 15 ns WS57C45-45 45 ns 25 ns
Return to Main Menu
2-21
WS57C45
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature............................-65 to + 150C Voltage on any Pin with Respect to Ground ................................-0.6V to +7V VPP with Respect to Ground...................-0.6V to + 14V ESD Protection ..................................................>2000V
*NOTICE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
OPERATING RANGE
RANGE Commercial Industrial Military TEMPERATURE 0C to +70C -40C to +85C -55C to +125C VCC +5V 10% +5V 10% +5V 10%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL VOL VOH ICC1 PARAMETER Output Low Voltage Output High Voltage VCC Active Current (CMOS) VCC Active Current (TTL) Input Leakage Current Output Leakage Current TEST CONDITIONS IOL = 16 mA IOH = -4 mA VCC = 5.5 V, f = 0 MHz (Note 1), Output Not Loaded Add 2 mA/MHz for AC Operation VCC = 5.5 V, f = 0 MHz (Note 1), Output Not Loaded Add 2 mA/MHz for AC Operation VIN = 5.5V or Gnd VOUT = 5.5 V or Gnd MIN 2.4 Comm'l Industrial Military Comm'l Industrial Military -10 -10 20 30 30 25 35 35 10 10 MAX 0.4 UNITS V V mA mA mA mA mA mA A A
ICC2 ILI ILO
NOTES:
1. CMOS inputs: GND 0.3V or VCC 0.3V. 2. TTL inputs: VIL 0.8V, VIH 2.0V.
3. This parameter is only sampled and is not 100% tested.
CAPACITANCE (4)
SYMBOL C IN C OUT PARAMETER Input Capacitance Output Capacitance CONDITIONS TA = 25C, f = 1 MHz, VCC = 5.0 V MAX 5 8 UNITS pF pF
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER Address Setup to Clock High Address Hold From Clock High Clock High to Valid Output Clock Pulse Width OES Setup to Clock High OES Hold From Clock High Delay From INIT to Valid Output INIT Recovery to Clock High INIT Pulse Width Active Output From Clock High Inactive Output From Clock High Active Output From OE Low Inactive Output From OE High SYMBOL t SA t HA t CO t PWC t SOES t HOES t DI t RI t PWI t LZC t HZC t LZOE t HZOE 15 15 15 15 15 15 15 12 5 20 20 20 20 20 20 20 WS57C45-25
MIN MAX
WS57C45-35
MIN MAX
WS57C45-45
MIN MAX
UNITS ns ns
25 0 12
35 0 15 20 15 5 20
45 0 25 20 15 5 35 20 25 30 30 30 30
ns ns ns ns ns ns ns ns ns ns ns
2-22
WS57C45
BLOCK DIAGRAM
INIT A10 A9 A8 A7 A6 A5 ROW DECODER 1 OF 64 64 X 256 PROGRAMMABLE ARRAY 8 X 1 OF 32 MULTIPLEXER
O7 O6 PROGRAMMABLE INITIALIZE WORD O5 8-BIT EDGETRIGGERED REGISTER O4 O3 O2 O1 CP PROGRAMMABLE MULTIPLEXER O0
A4 A3 A2 A1 A0 COLUMN DECODER 1 OF 32
OE/OES CP
D C
Q
TEST LOAD (High Impedance Test Systems)
98 2.01 V D.U.T.
A.C. TESTING INPUT/OUTPUT WAVEFORM
3.0 1.5 0.0 TEST POINTS
1.5
30 pF (INCLUDING SCOPE AND JIG CAPACITANCE)
A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V for a logic "0." Timing measurements are made at 1.5 V for input and output transitions in both directions.
AC READ TIMING DIAGRAM
tHA A0-A10 tSOES tHOES OES tSOES tPWC CP tPWC O0-O7 tCO OE tDI tRI tHZC tLZC tCO tHZOE tLZOE tPWC tPWC tHOES tPWC tPWC tSOES tHOES tSA tHA
INIT tPWI
2-23
WS57C45
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE
1.60 40.0 35.0 1.40 30.0 NORMALIZED I CC DELTA Taa (ns) 1.20 25.0 20.0 15.0 10.0 5.0 0.60 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE ( V ) 0.0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING
1.00
0.80
0.0
200
400
600
800
1000
CAPACITANCE ( pF )
NORMALIZED Taa vs. AMBIENT TEMPERATURE
1.6 1.2
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE
1.4 1.1 NORMALIZED Taa 1.2 NORMALIZED I CC
1.0
1.0
0.9 0.8
0.6 -55 -35 -15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (C )
0.8 -55 -35 -15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (C)
2-24
WS57C45
FUNCTION DESCRIPTION
The WS57C45 is an electrically programmable read only memory produced with WSI's patented high-performance self-aligned split gate CMOS EPROM technology. It is organized as 2048 x 8 bits and is pin-for-pin compatible with bipolar TTL fuse link PROMs. The WS57C45 includes a D-type 8-bit data register on-chip which reduces the complexity and cost of microprogrammed pipelined systems where PROM data is held temporarily in a register. The circuit features a programmable synchronous (OES ) or asynchronous (OE) output enable and asynchronous initialization (INIT). The programmed state of the enable pin (OES or OE) will dictate the state of gthe outputs at power up. If OES has been programmed, the outputs will be in the OFF or high impedance state. If OE has been programmed, the outputs will be OFF or high impedance only if the OE input is HIGH. Data is read by applying the address to inputs A10 - A0 and a LOW to the enable input. The data is retrieved and loaded into the master section of the 8-bit data register during the address set-up time. The data is transferred to the slave output of the data register at the next LOW to HIGH clock (CP) transition. Then the output buffers present the data on the outputs (O7 - O0). When using the asynchronous enable (OE), the output buffers may be disabled at any time by switching the enable input to a logic HIGH. They may be re-enabled by switching the enable to a logic LOW. When using the sychronous enable (OES), the outputs revert to a high impedance or OFF state at the next positive clock edge following the OES input transition to a HIGH state. The output will revert to the active state following a positive clock edge when the OES input is at a LOW state. The address and synchronous enable inputs are free to change following a positive clock edge since the output will not change until the next low to high clock transition. This enables accessing the next data location while previously addressed data is present on the outputs. To avoid race conditions and simplify system timing, the 8-bit edge triggered data register clock is derived directly from the system clock. The WS57C45 has an asynchronous initialize input (INIT). This function can be used during power-up and time-out periods to implement functions such as a start address or initialized bus control word. The INIT input enables the contents of a 2049th 8-bit word to be loaded directly into the output data register. The INIT input can be used to load any 8-bit data pattern into the register since each bit is programmable by the user. When unprogrammed, activating INIT will result in clearing the register (outputs LOW). When all bits are programmed, actrivating INIT results in PRESETting the register (outputs HIGH). When activated LOW, the INIT input results in an immediate load of the 2049th word into both the master and slave sections of the output register. This is independent of any other input including the clock (CP) input. The initialize data will be present at the outputs after the asynchronous enable (OE) is taken to a LOW state.
Programming Information
Apply power to the WS57C45 for normal read mode operation with CP/PGM, OE/OES and INIT/VPP at VIH. Then take INIT/VPP to VPP. The part is then in the program inhibit mode operation and the output lines are in a high impedance state. Refer to Figure 5. As shown in Figure 5, address, program and verify one byte of data. Repeat this sequence for each location to be programmed. When intelligent programming is used, the program pulse width is 1 ms in length. Each address location is programmed and verified until it verifies correctly up to and including 5 times. After the location verifies, an additional programming pulse should be applied that is X1 times in duration of the sum of the previous programming pulses before proceeding on to the next address and repeating the process.
Initialization Byte Programming
The WS57C45 has a 2049th byte of data that can be used to initialize the value of the data register. This byte contains the value "0" when it is shipped from the factory. The user must program the 2049th byte with a value other than "0" for data register initialization if that value is not desired. Except for the following details, the user may program the 2049th byte in the same manner as the other 2048 bytes. First, since all 2048 addresses are used up, a super voltage address feature is used to enable an additional address. The actual address includes VPP on A1 and VIL on A2. Refer to the Mode Selection table. The programming and verification of the Initial Byte is accomplished operationally by performing an initialize function.
2-25
WS57C45
Synchronous Enable Programming
The WS57C45 contains both a synchronous and asynchronous enable feature. The part is delivered configured in the asynchronous mode and only requires alteration if the synchronous mode is required. This is accomplished by programming an on-chip EPROM cell. Similar to the Initial Byte, this function is enabled and addressed by using a super voltage. Referring to the Mode Selection table, VPP is applied to A1 followed by VIH applied to A2. This procedure addresses the EPROM cell that programs the synchronous enable feature. The EPROM cell is programmed with a 10 ms program pulse on CP/PGM. It does not require any data since there is no selection as to how synchronous enable may be programmed, only if it is to be programmed.
Synchronous Enable Verification
The WS57C45's synchronous enable function is verified operationally. Apply power for read operation with OE/OES and INIT/VPP at VIH and take the clock (CP/PGM) from VIL to VIH. The output data bus should be in a high impedance state. Next take OE/OES to VIL. The outputs will remain in the high impedance state. Take the clock (CP/PGM) from VIL to VIH and the outputs will now contain the data that is present. Take OE/OES to VIH. The output should remain driven. Clocking CP/PGM once more from VIL to VIH should place the outputs again in a high impedance state.
Blank Check
Upon delivery from WaferScale Integration, Inc. or after each erasure (see Erasure section), the WS57C45 has all 2048 bytes in the `0' state. "1's" are loaded into the WS57C45 through the procedure of programming.
PIN FUNCTION MODE READ OR OUTPUT DISABLE A2 X X X X X X VIH VIL X CP/PGM X X VIL VIH VIH VIL VIL VIL X (OE/OES)/VFY VIL VIH VIH VIL VIH VIH VIH VIH VIL INIT/VPP VIH VIH VPP VPP VPP VPP VPP VPP VIL A1 X X X X X X VPP VPP X
OUTPUTS Data Out High Z Data In Data Out High Z Data In High Z Data In Data Out
Read (Note 6) Output Disable Program (Notes 5 & 7) Program Verify (Notes 5 & 7) Program Inhibit (Notes 5 & 7) Intelligent Program (Notes 5 & 7) Program Synch Enable (Note 7) Program Initial Byte (Note 7) Initial Byte Read
NOTES: 5. X = Don't Care but not to exceed VPP. 6. During read operation, the output latches are loaded on a "0" to "1" transition of CP. 7. During programming and verification, all unspecified pins to be at VIL.
2-26
WS57C45
FIGURE 5. PROM PROGRAMMING WAVEFORMS
PROGRAM OTHER BYTES PROGRAM VIH ADDRESS VIL ADDRESS STABLE t AS t DS VIH DATA VIL INIT/VPP VPP t AH VIH VIL VIH CP/PGM VIL VIH (OE/OES)/VFY VIL t DV t VP tR t PW t AS DATA IN t DH DATA OUT t DZ tF t DV VERIFY
FIGURE 6. INITIAL BYTE PROGRAMMING WAVEFORMS
VIH VIL VPP VIH VIL VIH DATA VIL VPP INIT/VPP VIH VIL VIH CP/PGM VIL tAS tR tPW tAH tF tR DATA IN A1 tDS tDH tF A2 PROGRAM
FIGURE 7. PROGRAM SYNCHRONOUS ENABLE
VIH VIL t AS VIH CP/PGM VIL VIH VIL tR VPP VIH VIL VPP INIT/VPP VIH VIL tF A1 tR t AH tAS t PW t AH A2
(OE/OES)/ VFY
tF
2-27
WS57C45
PROGRAMMING INFORMATION DC CHARACTERISTICS (TA = 25 5C, VCC = 5.6 V 0.25 V, VPP = 13.5 0.5 V)
SYMBOLS ILI IPP ICC VIL VIH VOL VOH PARAMETER Input Leakage Current (VIN = VCC or Gnd) VPP Supply Current During Programming Pulse VCC Supply Current Input Low Voltage Input High Voltage Output Low Voltage During Verify (IOL = 16 mA) Output High Voltage During Verify (IOH = -4 mA) 2.4 -0.1 2.0 MIN -10 MAX 10 60 25 0.8 VCC + 0.3 0.45 UNITS A mA mA V V V V
NOTE: 8. VPP must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA = 25 5C, VCC = 5.6 V 0.25 V, VPP = 13.5 0.5 V)
SYMBOLS t PW tAS tDS tAH tDH tR, tF tVD tVP tDV tDZ PARAMETER Programming Pulse Width Address Setup Time Data Setup Time Address Hold Time Data Hold Time VPP Rise and Fall Time Delay to VFY VFY Pulse Width VFY Data Valid VFY HIGH to High Z MIN 0.1 1.0 1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 MAX 10 UNITS ms s s s s s s s s s
2-28
WS57C45
ORDERING INFORMATION
PART NUMBER WS57C45-25T WS57C45-35KMB* WS57C45-35S WS57C45-35T WS57C45-35TMB* WS57C45-45KMB* WS57C45-45TMB* SPEED (ns) 25 35 35 35 35 45 45 PACKAGE TYPE 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" 24 Pin Plastic DIP, 0.3" 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" OPERATING WSI PACKAGE TEMPERATURE MANUFACTURING DRAWING RANGE PROCEDURE T1 K1 S1 T1 T1 K1 T1 Comm'l Military Comm'l Comm'l Military Military Military Standard MIL-STD-883C Standard Standard MIL-STD-883C MIL-STD-883C MIL-STD-883C
NOTE: The actual part marking will not include the initials "WS."
*SMD product. See section 4 for DESC SMD numbers.
PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS REFER TO PAGE 5-1
The WS57C45 is programmed using Algorithm A shown on page 5-3.
Return to Main Menu
2-29

▲Up To Search▲

Price & Availability of WS57C45-25

	To Download WS57C45-25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .